MC68HC08BD24 Datasheet, PDF (228/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
18.6.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Figure 18-3. Break Address Register High (BRKH)
Address: $FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 18-4. Break Address Register Low (BRKL)
18.6.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Technical Data
228
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor