MC68HC08BD24 Datasheet, PDF (108/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode.
Table 9-1. Mode Selection
Mode
OSCOUT
Bus
Frequency
V_TST
V_TST
1011
Monitor
1010
Monitor
O-----S----C----X-----C----L---K---
2
OSCXCLK
O-----S----C----X-----C----L---K---
4
O-----S----C----X-----C----L---K---
2
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The OSCOUT frequency is
equal to the OSCXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU monitor mode firmware then sends a break
signal (10 consecutive logic zeros) to the host computer, indicating that
it is ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
Monitor mode uses different vectors for reset and SWI. The alternate
vectors are in the $FE page instead of the $FF page and allow code
execution from the internal monitor firmware instead of user code.
When the host computer has completed downloading code into the MCU
RAM, This code can be executed by driving PTA0 low while asserting
RST low and then high. The internal monitor ROM firmware will interpret
the low on PTA0 as an indication to jump to RAM, and execution control
will then continue from RAM. Execution of an SWI from the downloaded
code will return program control to the internal monitor ROM firmware.
Technical Data
108
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor