MC68HC08BD24 Datasheet, PDF (96/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-14. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
Cycles
IDB $A6 $A6
$A6
RST
OSCXCLK
32
Cycles
RST VCT H RST VCT L
Figure 7-15. Wait Recovery from Internal Reset
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in configuration register 1 (CONFIG1). If
SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCXCLK cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
Technical Data
96
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor