MC68HC08BD24 Datasheet, PDF (41/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Addr.
$003C
$003D
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
Register Name
Bit 7
6
5
Read:
R
R
R
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
Sync Processor Control ^Read: _{VSIE VEDGE} ^VSIF
and Status Register Write:
0
(SPCSR) _{Reset: 0}
0
0
Vertical Frequency High ^{Read: VOF}
Register Write:
(VFHR) _{Reset: 0}
0
CPW1
0
0
CPW0
0
Vertical Frequency Low ^{Read: VF7}
VF6
VF5
Register Write:
(VFLR) _{Reset: 0}
0
0
Hsync Frequency High ^Read:
Register Write:
(HFHR) _Reset:
HFH7
0
HFH6
0
HFH5
0
Hsync Frequency Low ^{Read: HOVER}
0
0
Register Write:
(HFLR) _{Reset: 0}
0
0
Sync Processor I/O ^{Read: VSYNCS}
Control Register Write:
(SPIOCR) _{Reset: 0}
HSYNCS
0
COINV
0
= Unimplemented
4
3
2
1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
COMP
0
VF12
VINVO HINVO
0
0
VF11 VF10
VPOL
0
VF9
0
0
0
0
VF4
VF3
VF2
VF1
0
HFH4
0
HFH3
0
HFH2
0
HFH1
0
HFL4
0
HFL3
0
HFL2
0
HFL1
0
0
0
0
R
SOGSEL CLAMPOE BPOR
0
0
0
0
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
Bit 0
R
R
R
R
HPOL
0
VF8
0
VF0
0
HFH0
0
HFL0
0
SOUT
0
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
41