MC68HC08BD24 Datasheet, PDF (151/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

12.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $005F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-4. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 12-3
shows the available clock configurations. The ADC clock should be
set to approximately 1MHz. With an internal bus frequency of 6MHz,
set ADIV[2:0] = 010, for a divide by four ADC clock rate.
Table 12-3. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
151