MC68HC08BD24 Datasheet, PDF (181/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

14.6.3 Vertical Frequency Registers (VFRs)
This register pair contains the 13-bit vertical frequency count value, an
overflow bit, and the clamp pulse width selection bits.
Address: $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read: VOF
0
0
VF12 VF11 VF10
VF9
VF8
Write:
CPW1 CPW0
Reset: 0
0
0
0
0
0
0
0
Figure 14-5. Vertical Frequency High Register
Address: $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-6. Vertical Frequency Low Register
VF[12:0] — Vertical Frame Frequency\
This read-only 13-bit contains information of the vertical frame
frequency. An internal 13-bit counter counts the number of 8µs
periods between two Vsync pulses. The most significant 5 bits of the
counted value is transferred to the high byte register, and the least
significant 8 bits is transferred to an intermediate buffer. When the
high byte register is read, the 8-bit counted value stored in the
intermediate buffer will be uploaded to the low byte register.
Therefore, user program must read the high byte register first, then
low byte register in order to get the complete counted value of one
vertical frame. If the counter overflows, the overflow flag, VOF, will be
set, indicating the counter value stored in the VFRs is meaningless.
The data corresponds to the period of one vertical frame. This register
can be read to determine if the frame frequency is valid, and to
determine the video mode.
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
181