MC68HC08BD24 Datasheet, PDF (138/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Combining the 5-bit PWM together with the 3-bit BRM, the average duty
cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit
PWM portion, and N is the content of the 3-bit BRM portion. Using this
mechanism, a true 8-bit resolution PWM type DAC with reasonably high
repetition rate can be obtained.
The value of each PWM Data Register is continuously compared with
the content of an internal counter to determine the state of each PWM
channel output pin. Double buffering is not used in this PWM design.
Addr.
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Table 11-1. PWM I/O Register Summary
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PWM0 Data Register
(0PWM)
Read:
Write:
0PWM4
0PWM3
0PWM2 0PWM1 0PWM0
0BRM2
0BRM1
0BRM0
PWM1 Data Register
(1PWM)
Read:
Write:
1PWM4
1PWM3
1PWM2 1PWM1 1PWM0
1BRM2
1BRM1
1BRM0
PWM2 Data Register
(2PWM)
Read:
Write:
2PWM4
2PWM3
2PWM2 2PWM1 2PWM0
2BRM2
2BRM1
2BRM0
PWM3 Data Register
(3PWM)
Read:
Write:
3PWM4
3PWM3
3PWM2 3PWM1 3PWM0
3BRM2
3BRM1
3BRM0
PWM4 Data Register
(4PWM)
Read:
Write:
4PWM4
4PWM3
4PWM2 4PWM1 4PWM0
4BRM2
4BRM1
4BRM0
PWM5 Data Register
(5PWM)
Read:
Write:
5PWM4
PWM6 Data Register
(6PWM)
Read:
Write:
6PWM4
5PWM3
6PWM3
5PWM2
6PWM2
5PWM1
6PWM1
5PWM0
6PWM0
5BRM2
6BRM2
5BRM1
6BRM1
5BRM0
6BRM0
PWM7 Data Register
(7PWM)
Read:
Write:
7PWM4
7PWM3
7PWM2 7PWM1 7PWM0
7BRM2
7BRM1
7BRM0
PWM Control Read:
Register 1
PWM7E
(PWMCR1) ^Write:
PWM6E
PWM5E
PWM4E
PWM3E
PWM2E
PWM1E
PWM0E
Reset: 0
0
0
0
0
0
0
0
Technical Data
138
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor