MC68HC08BD24 Datasheet, PDF (79/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

RESET
PIN LOGIC
STOP/WAIT
CONTROL
SIM
COUNTER
CLOCK
CONTROL
÷2
CLOCK GENERATORS
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
OSCXCLK (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 7-1. SIM Block Diagram
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
79