MC68HC08BD24 Datasheet, PDF (140/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

11.4.1 PWM Data Registers 0 to 15 (0PWM–15PWM)
Address:
$0020–$0027 and $0051–$0058
Bit 7
6
5
4
3
2
1
Bit 0
Read:
xPWM4 xPWM3 xPWM2 xPWM1
Write:
xPWM0
xBRM2
xBRM1
xBRM0
Reset: 0
0
0
0
0
0
0
0
Figure 11-1. PWM Data Registers 0 to 15 (0PWM–15PWM)
The output waveform of the 16 PWM channels are each configured by
an 8-bit register, which contains a 5-bit PWM in MSB portion and a 3-bit
binary rate multiplier (BRM) in LSB portion
xPWM4–xPWM0 — PWM Bits
The value programmed in the 5-bit PWM portion will determine the pulse
length of the output. The clock to the 5-bit PWM portion is the system
clock (CPU clock), the repetition rate of the output is hence f_OP ÷ 32.
Examples of PWM output waveforms are shown in Figure 11-3.
xBRM2–xBRM0 — Binary Rate Multiplier Bits
The 3-bit BRM will generate a number of narrow pulses which are
equally distributed among an 8-PWM-cycle frame. The number of pulses
generated is equal to the number programmed in the 3-bit BRM portion.
Examples of PWM output waveforms are shown in Figure 11-3.
Technical Data
140
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor