MC68HC08BD24 Datasheet, PDF (91/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

The LDA opcode is pre-fetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI pre-fetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-4 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
91