MC68HC08BD24 Datasheet, PDF (155/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Table 13-2. DDC I/O Register Summary
Addr. Register Name
Bit 7
6
5
4
3
DDC Master Control ^Read: _ALIF
NAKIF
BB
MAST MRW
$0016
Register Write:
(DMCR) _Reset:
0
0
0
0
0
$0017
DDC Address Register
(DADR)
Read:
Write:
Reset:
DAD7
1
DAD6
0
DAD5
1
DAD4
0
DAD3
0
$0018
DDC ^Read: _DEN
DIEN
0
Control Register Write:
(DCR) _Reset:
0
0
0
0
TXAK
0
0
$0019
DDC ^{Read: RXIF}
Status Register Write: 0
(DSR) _Reset:
0
TXIF MATCH SRW
0
0
0
0
RXAK
1
$001A
DDC
Data Transmit Register
(DDTR)
Read:
Write:
Reset:
$001B
DDC
Data Receive Register
(DDRR)
Read:
Write:
Reset:
DTD7
1
DRD7
0
DTD6
1
DRD6
0
DTD5
1
DRD5
0
DTD4
1
DRD4
0
DTD3
1
DRD3
0
$001C
DDC2 Address Register
(D2ADR)
Read:
Write:
Reset:
D2AD7
0
D2AD6
0
D2AD5
0
D2AD4
0
D2AD3
0
= Unimplemented
2
1
BR2
BR1
0
0
DAD2 DAD1
0
0
SCLIEN DDC1EN
0
SCLIF
0
0
0
TXBE
1
DTD2 DTD1
1
DRD2
1
DRD1
0
0
D2AD2 D2AD1
0
0
Bit 0
BR0
0
EXTAD
0
0
0
RXBF
0
DTD0
1
DRD0
0
0
0
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
155