MC68HC08BD24 Datasheet, PDF (185/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

14.6.5 Sync Processor Control Register 1 (SPCR1)
Address: $0046
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LVSIF
LVSIE
HPS1 HPS0
R
Write:
0
R
ATPOL FSHF
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 14-9. Sync Processor Control Register 1 (SPCR1)
LVSIE — Low VSync Interrupt Enable
When this bit is set, the LVSIF flag is enabled to generate an interrupt
request to the CPU. When LVSIE is cleared, the LVSIF flag is
prevented from generating an interrupt request to the CPU. Reset
clears this bit.
1 = Low Vsync interrupt enabled
0 = Low Vsync interrupt disabled
LVSIF — Low VSync Interrupt Flag
This read-only bit is set when the value of VFR is higher than $C00
(vertical frame frequency below 40.7Hz). LVSIF generates an
interrupt request to the CPU if the LVSIE is also set. This bit is cleared
by writing a "0" to it or reset.
1 = Vertical frequency is below 40.7Hz
0 = Vertical frequency is higher than 40.7Hz
HPS[1:0] — HSYNC input Detection Pulse Width
These two bits control the detection pulse width of HSYNC input.
Reset clears these two bits, setting a default middle frequency of
HSYNC input.
Table 14-8. HSYNC Polarity Detection Pulse Width
HPS1
0
1
0
HPS0
0
X
1
Polarity Detection Pulse Width
Long > 7µs and Short < 6µs
Long > 3.5µs and Short < 3µs
Long > 14µs and Short < 12µs
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
185