MC68HC08BD24 Datasheet, PDF (213/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
ACK
RESET
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
CLR
D
Q
CK
IRQ
FF
SYNCHRO-
NIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 16-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr
$001E
Table 16-1. IRQ I/O Register Summary
Register Name
Bit 7
6
5
Read: 0
0
0
IRQ Status and Control
Register (INTSCR)
Write:
Reset: 0
0
0
= Unimplemented
4
3
0
IRQF
0
0
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
213