MC68HC08BD24 Datasheet, PDF (116/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

10.2 Introduction
This section describes the timer interface module (TIM2, Version B). The
TIM is a two-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions. Figure
10-1 is a block diagram of the TIM.
10.3 Features
Features of the TIM include the following:
• Two Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
• Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
• Programmable TIM Clock Input
– Seven-Frequency Internal Bus Clock Prescaler Selection
• Free-Running or Modulo Up-Count Operation
• Toggle Any Channel Pin on Overflow
• TIM Counter Stop and Reset Bits
• Modular Architecture Expandable to Eight Channels
NOTE:
TCH1 (timer channel 1) is not bonded to an external pin on this MCU.
Therefore, any references to the timer TCH1 pin in the following text
should be interpreted as not available — but the internal status and
control registers are still available.
10.4 Pin Name Conventions
The TIM share one I/O pin with one port E I/O pin. The full name of the
TIM I/O pin is listed in Table 10-1. The generic pin name appear in the
text that follows.
Table 10-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
PTE0/SOG/TCH0
TCH1
Not Available
Technical Data
116
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor