MC68HC08BD24 Datasheet, PDF (174/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

14.5.1 Polarity Detection
14.5.1.1 Hsync Polarity Detection
The Hsync polarity detection circuit measures the length of high and low
period of the HSYNC input. If the length of high is longer than L and the
length of low is shorter than S, the HPOL bit will be "0", indicating a
negative polarity HSYNC input. If the length of low is longer than L and
the length of high is shorter than S, the HPOL bit will be "1", indicating a
positive polarity HSYNC input. The table below shows three possible
cases for HSYNC polarity detection — the conditions are selected by the
HPS[1:0] bits in the Sync Processor Control Register 1 (SPCR1).
Polarity Detection Pulse Width
Long is greater than (L) Short is less than (S)
7 µs
6 µs
3.5 µs
3 µs
14 µs
12 µs
SPCR1 ($0046)
HPS1
HPS0
0
0
1
X
0
1
14.5.1.2 Vsync Polarity Detection
The Vsync polarity detection circuit performs a similar function as for
Hsync. If the length of high is longer than 4ms and the length of low is
shorter than 2ms, the VPOL bit will be "0", indicating a negative polarity
VSYNC input. If the length of low is longer than 4ms and the length of
high is shorter than 2ms, the VPOL bit will be "1", indicating a positive
polarity VSYNC input.
14.5.1.3 Composite Sync Polarity Detection
When a composite sync signal is the input (COMP = 1 for composite
sync processing), the HPOL bit = VPOL bit, and the polarity is detected
using the VSYNC polarity detection criteria described in section
14.5.1.2.
Technical Data
174
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor