MC68HC08BD24 Datasheet, PDF (187/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

HVOCR
000
001
010
011
100
101
110
111
HVOCR[2:0] — H&V Output Select Bits
These three bits select the frequencies of the internal generated
free-running sync pulses for output to HSYNCO and VSYNCO pins,
when the SOUT bit is set in the SPIOCR. Reset clears these bits,
setting a default horizontal frequency of 31.25kHz and a vertical
frequency of 60Hz, a video mode of 640×480.
Table 14-10. Free-Running HSYNC and VSYNC Options
HSYNCO
Pulse width
Frequency
Negative 2µs
31.25 kHz
Negative 2µs
43.48 kHz
Negative 2µs
48.78 kHz
Negative 2µs
54.05 kHz
Negative 2µs
60.61 kHz
Negative 2µs
80.00 kHz
Negative 2µs
90.91 kHz
Negative 2µs
105.26 kHz
VSYNCO
Pulse width
Frequency
Negative 192µs
59.98 Hz
Negative 138µs
84.92 Hz
Negative 123µs
60.00 Hz
Negative 111µs
84.98 Hz
Negative 99µs
75.01 Hz
Negative 75µs
74.98 Hz
Negative 66µs
84.96 Hz
Negative 57µs
85.02 Hz
Video Mode
640 × 480
640 × 480
1024 × 768
800 × 600
1024 × 768
1280 × 1024
1280 × 1024
1600 × 1200
14.7 System Operation
This Sync Processor is designed to assist in determining the video mode
of incoming HSYNC and VSYNC of various frequencies and polarities,
and DPMS modes. In the DPMS standard, a no sync pulses definition
can be detected when the value of the Hsync Frequency Register (the
number of Hsync pulses) is less than one or when the VOF bit is set.
Since the Hsync Frequency Register is updated repeatedly in every
32.768ms, and a valid Vsync must have a frequency greater than
40.7Hz, a valid Vsync pulse will arrive within the 32.768ms window.
Therefore, the user should read the Hsync Frequency Register every
32.768ms to determine the presence of Hsync and/or Vsync pulses.
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
187