MC68HC08BD24 Datasheet, PDF (218/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

17.3 Functional Description
Figure 17-1 shows the structure of the COP module.
OSCXCLK
12-BIT COP PRESCALER
RESET CIRCUIT
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 17-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2¹⁸ – 2⁴ or 2¹³ – 2⁴
OSCXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in configuration register 1. With a 2¹⁸ – 2⁴ OSCXCLK cycle
overflow option, a 24MHz crystal gives a COP timeout period of
10.922ms. Writing any value to location $FFFF before an overflow
occurs prevents a COP reset by clearing the COP counter and stages
12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Technical Data
218
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor