MC68HC08BD24 Datasheet, PDF (167/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

(a) Master Transmit Mode
START
Address 0 ACK
TX Data1
ACK
TX DataN
NAK STOP
TXBE=0
MRW=0
MAST=1
Data1 → DDTR
TXBE=1
TXIF=1
Data2 → DDTR
TXBE=1
TXIF=1
Data3 → DDTR
(b) Master Receive Mode
START
Address 1 ACK
RX Data1
ACK
TXBE=1 NAKIF=1
TXIF=1 MAST=0
DataN+2 → DDTR TXBE=0
RX DataN
NAK STOP
RXBF=0
MRW=1
MAST=1
TXBE=0
(dummy data → DDTR)
Data1 → DDRR
RXIF=1
RXBF=1
(c) Slave Transmit Mode
START
Address 1 ACK
TX Data1
ACK
DataN → DDRR NAKIF=1
RXIF=1 ^MAST=0
RXBF=1
TX DataN
NAK STOP
TXBE=1
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=1
Data1 → DDTR
TXBE=1
TXIF=1
Data2 → DDTR
(d) Slave Receive Mode
START
Address 0 ACK
RX Data1
ACK
TXBE=1 NAKIF=1
TXIF=1 ^TXBE=0
DataN+2 → DDTR
RX DataN
NAK STOP
TXBE=0
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=0
Data1 → DDRR
RXIF=1
RXBF=1
KEY: shaded data packets indicate a transmit by the MCU’s DDC module
DataN → DDRR
RXIF=1
RXBF=1
Figure 13-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
167