MC68HC08BD24 Datasheet, PDF (55/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

5.4 Configuration Register 1
The CONFIG1 register is used in the initialization of various MCU
options. It can only be written once after each reset. All of the CONFIG1
register bits are cleared during reset. Since the various options affect the
operation of the MCU, it is recommended that the CONFIG1 register be
written immediately after reset.
Address: $001F
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
SSREC COPRS STOP
Write:
Reset: 0
0
0
0
0
0
0
Register is write-once after reset.
= Unimplemented
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
OSCXCLK cycles instead of a 4096-OSCXCLK cycle delay.
1 = Stop mode recovery after 32 OSCXCLK cycles
0 = Stop mode recovery after 4096 OSCXCLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 17. Computer Operating Properly (COP).)
1 = COP timeout period = 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
55