MC68HC08BD24 Datasheet, PDF (81/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-2.
From
SIM
SIMOSCEN
OSC1
OSCXCLK
÷ 2 ^OSCOUT
OSCILLATOR
OSC2
Figure 7-2. OSC Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(OSCXCLK) divided by four.
7.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 OSCXCLK cycle POR timeout has completed. The RST is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the timeout.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode (by an interrupt, break, or reset), the SIM
allows OSCXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 OSCXCLK cycles. (See 7.7.2 Stop
Mode.)
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
81