MC68HC08BD24 Datasheet, PDF (172/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Table 14-2. Sync Processor I/O Register Summary
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0040 ^{Sync Processor Control Read:} VSIE
and Status Register Write:
(SPCSR) _Reset:
0
$0041 ^{Vertical Frequency High Read: VOF}
Register Write:
(VFHR) _Reset:
0
$0042 ^{Vertical Frequency Low Read: VF7}
Register Write:
(VFLR) _Reset:
0
VEDGE
0
0
CPW1
0
VF6
VSIF
0
0
0
CPW0
0
VF5
0
0
COMP VINVO HINVO
0
0
0
VF12 VF11 VF10
0
0
0
VF4
VF3
VF2
0
0
0
VPOL
0
VF9
0
VF1
0
HPOL
0
VF8
0
VF0
0
$0043
Hsync Frequency High
Register
(HFHR)
Read:
Write:
Reset:
HFH7
0
HFH6
0
$0044 ^{Hsync Frequency Low Read: HOVER}
0
Register Write:
(HFLR) _Reset:
0
0
$0045
Sync Processor I/O
Control Register
(SPIOCR)
Read:
Write:
Reset:
VSYNCS
0
HSYNCS
0
HFH5
0
0
0
COINV
0
HFH4 HFH3 HFH2 HFH1
0
HFL4
0
HFL3
0
HFL2
0
HFL1
0
0
0
0
R
SOGSEL CLAMPOE BPOR
0
0
0
0
HFH0
0
HFL0
0
SOUT
0
$0046
Sync Processor Control
Register 1
(SPCR1)
Read:
Write:
Reset:
$0047
H&V Sync Output
Control Register
(HVOCR)
Read:
Write:
Reset:
LVSIE
0
R
0
LVSIF
0
0
0
HPS1
0
0
0
0
= Unimplemented
HPS0
0
0
0
R
R
ATPOL FSHF
0
0
0
0
0
HVOCR2 HVOCR1 HVOCR0
0
0
0
0
R = Reserved
Technical Data
172
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor