MC68HC08BD24 Datasheet, PDF (162/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

13.6.5 DDC Status Register (DSR)
Address: $0019
Bit 7
6
5
4
3
2
1
Read: RXIF
Write: 0
TXIF MATCH SRW
0
RXAK
SCLIF
0
TXBE
Reset: 0
0
0
0
1
0
1
= Unimplemented
Figure 13-5. DDC Status Register (DSR)
Bit 0
RXBF
0
RXIF — DDC Receive Interrupt Flag
This flag is set after the data receive register (DDRR) is loaded with a
new received data. Once the DDRR is loaded with received data, no
more received data can be loaded to the DDRR register until the CPU
reads the data from the DDRR to clear RXBF flag. RXIF generates an
interrupt request to CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset; or when the DEN = 0.
1 = New data in data receive register (DDRR)
0 = No data received
TXIF — DDC Transmit Interrupt Flag
This flag is set when data in the data transmit register (DDTR) is
downloaded to the output circuit, and that new data can be written to
the DDTR. TXIF generates an interrupt request to CPU if the DIEN bit
in DCR is also set. This bit is cleared by writing "0" to it or when the
DEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MATCH — DDC Address Match
This flag is set when the received data in the data receive register
(DDRR) is an calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DADR register.
1 = Received address matches DADR
0 = Received address does not match
Technical Data
162
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor