MC68HC08BD24 Datasheet, PDF (78/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

7.7.1
7.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . 98
7.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . 99
7.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 100
7.2 Introduction
This section describes the system integration module, which supports up
to 16 external and/or internal interrupts. Together with the CPU, the SIM
controls all MCU activities. A block diagram of the SIM is shown in
Figure 7-1. Table 7-1 shows a summary of the SIM I/O registers. The
SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Technical Data
78
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor