MC68HC08BD24 Datasheet, PDF (184/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

HFH[7:0], HFL[4:0] — Horizontal Line Frequency
This read-only 13-bit contains the number of horizontal lines in a
32ms window. An internal 13-bit counter counts the Hsync pulses
within a 32ms window in every 32.768ms period. If the FSHF bit in
SPCR1 is set, only the most 11-bits (HFH[7:0] & HFL[4:2]) will be
updated by the counter. Thus, providing a Hsync pulse count in a 8ms
window in every 8.192ms.
The most significant 8 bits of counted value is transferred to the high
byte register, and the least significant 5 bits is transferred to an
intermediate buffer. When the high byte register is read, the 5-bit
counted value stored in the intermediate buffer will be uploaded to the
low byte register. Therefore, user the program must read the high byte
register first then low byte register in order to get the complete
counted value of Hsync pulses. If the counter overflows, the overflow
flag, HOVER, will be set, indicating the number of Hsync pulses in
32ms are more than 8191 (2¹³â€“1), i.e. a Hsync frequency greater
than 256kHz.
For the 32ms window, the HFHR and HFLR are such that the
frequency step unit in the 5-bit of HFLR is 0.03125kHz, and the step
unit in the 8-bit HFHR is 1kHz. Therefore, the Hsync frequency can
be easily calculated by:
Hsync Frequency = [HFH + (HFL × 0.03125)]kHz
where: HFH is the value of HFH[7:0]
HFL is the value of HFL[4:0]
HOVER — Hsync Frequency Counter Overflow
This read-only bit is set when an overflow has occurred on the 13-bit
Hsync frequency counter. Reset clears this bit, and will be updated
every count period.
An overflow occurs when the number Hsync pulses exceed 8191, a
Hsync frequency greater than 256kHz.
1 = A Hsync frequency counter overflow has occurred
0 = No Hsync frequency counter overflow has occurred
Technical Data
184
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor