MC68HC08BD24 Datasheet, PDF (205/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

15.6.3 Port D Options
The port D configuration register (PDCR) selects the port D pins for
module function or as standard I/O function.
Address: $0049
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
CLAMPE DDCSCLE DDCDATE
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-15. Port D Configuration Register (PDCR)
CLAMP — CLAMP Pin Enable
This bit is set to configure the PTD4/CLAMP pin for sync processor
clamp pulse output. Reset clears this bit.
1 = PTD4/CLAMP pin configured as CLAMP pin
0 = PTD4/CLAMP pin configured as standard I/O pin
DDCSCLE — DDC Clock Pin Enable
This bit is set to configure the PTD3/DDCSCL pin for DDCSCL
function. Reset clears this bit.
1 = PTD3/DDCSCL pin configured as DDCSCL pin
0 = PTD3/DDCSCL pin configured as standard I/O port
DDCDATE — DDC Data Pin Enable
This bit is set to configure the PTD2/DDCSDA pin for DDCSDA
function. Reset clears this bit.
1 = PTD2/DDCSDA pin configured as DDCSDA pin
0 = PTD2/DDCSDA pin configured as standard I/O port
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
205