MC68HC08BD24 Datasheet, PDF (37/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Addr.
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
Register Name
Bit 7
6
5
4
3
2
1
TIM Channel 1 ^Read: _Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Register High Write:
(TCH1H) _Reset:
Indeterminate after reset
TIM Channel 1 ^Read: _Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Register Low Write:
(TCH1L) _Reset:
Indeterminate after reset
Read:
DDC Master Control
Register (DMCR)
Write:
ALIF
NAKIF
BB
MAST MRW
BR2
BR1
Reset: 0
0
0
0
0
0
0
Read:
DDC Address Register
(DADR)
Write:
Reset:
DAD7
1
DAD6
0
DAD5
1
DAD4
0
DAD3
0
DAD2
0
DAD1
0
Read:
0
DDC Control Register
(DCR)
Write:
DEN
DIEN
Reset: 0
0
0
0
TXAK SCLIEN DDC1EN
0
0
0
0
Read: RXIF
DDC Status Register
(DSR)
Write:
0
Reset: 0
TXIF MATCH SRW
0
0
0
0
RXAK
1
SCLIF
0
0
TXBE
1
DDC ^Read:
Data Transmit Register Write:
(DDTR) _Reset:
DTD7
1
DTD6
1
DTD5
1
DTD4
1
DTD3
1
DTD2
1
DTD1
1
DDC Read:
Data Receive Register
(DDRR)
Write:
Reset:
DRD7
0
DRD6
0
DRD5
0
DRD4
0
DRD3
0
DRD2
0
DRD1
0
Read:
DDC2 Address Register
(D2ADR)
Write:
Reset:
D2AD7
0
D2AD6
0
D2AD5
0
D2AD4
0
D2AD3
0
D2AD2
0
D2AD1
0
Read:
0
0
0
0
Configuration Register 0
(CONFIG0)
Write:
HSYNCOE
VSYNCOE
SOGE
Reset: 0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Bit 0
Bit8
Bit0
BR0
0
EXTAD
0
0
0
RXBF
0
DTD0
1
DRD0
0
0
0
0
0
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
37