MC68HC08BD24 Datasheet, PDF (215/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
16.6 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Section 18. Break
Module (BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
16.7 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
215