MC68HC08BD24 Datasheet, PDF (88/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

7.6.1 Interrupts
MODULE
INTERRUPT
I BIT
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-9 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-7 shows interrupt entry timing. Figure
7-8 shows interrupt recovery timing.
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE
INTERRUPT
I BIT
Figure 7-7. Interrupt Entry
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
R/W
Figure 7-8. Interrupt Recovery
Technical Data
88
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor