MC68HC08BD24 Datasheet, PDF (198/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-4 summarizes
the operation of the port B pins.
Table 15-4. Port B Pin Functions
DDRB Bit PTB Bit
I/O Pin Mode
0
X⁽¹⁾
Input, Hi-Z⁽²⁾
Accesses
to DDRB
Read/Write
DDRB7–DDRB0
1
X
Output
DDRB7–DDRB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
PTB7–PTB0
Write
PTB7–PTB0⁽³⁾
PTB7–PTB0
15.4.3 Port B Options
The PWM control register 1 (PWMCR1) selects the port B pins for PWM
function or as standard I/O function. See 11.4.2 PWM Control
Registers 1 and 2 (PWMCR1:PWMCR2).
Address: $0028
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PWM7E PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 15-8. PWM Control Register 1 (PWMCR1)
PWM7E–PWM0E — PWM Output Enable 7–0
Setting a bit to "1" will configure the corresponding PTBx/PWMx pin
for PWM output function. Reset clears these bits.
1 = PTBx/PWMx pin configured as PWMx output pin
0 = PTBx/PWMx pin configured as standard I/O pin
Technical Data
198
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor