MC68HC08BD24 Datasheet, PDF (156/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

13.5 DDC Protocols
In DDC1 protocol communication, the module is in transmit mode. The
data written to the transmit register is continuously clocked out to the
SDA line by the rising edge of the Vsync input signal. During DDC1
communication, a falling transition on the SCL line can be detected to
generate an interrupt to the CPU for mode switching.
In DDC2AB protocol communication, the module can be either in
transmit mode or in receive mode, controlled by the calling master.
In DDC2 protocol communication, the module will act as a standard IIC
module, able to act as a master or a slave device.
13.6 Registers
Seven registers are associated with the DDC module, they outlined in
the following sections.
13.6.1 DDC Address Register (DADR)
Address:
Read:
Write:
Reset:
$0017
Bit 7
DAD7
1
6
DAD6
0
5
DAD5
1
4
DAD4
0
3
DAD3
0
2
DAD2
0
1
DAD1
0
Figure 13-1. DDC Address Register (DADR)
Bit 0
EXTAD
0
DAD[7:1] — DDC Address
These 7 bits can be the DDC2 interface’s own specific slave address
in slave mode or the calling address when in master mode. Reset sets
a default value of $A0.
Technical Data
156
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor