MC68HC08BD24 Datasheet, PDF (146/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

or DDR will not have any affect on the port pin that is selected by the
ADC. Read of a port pin which is in use by the ADC will return an
unknown state if the corresponding DDR bit is at logic 0. If the DDR bit
is at logic 1, the value in the port data latch is read.
12.4.2 Voltage Conversion
When
the
input
voltage
to
the
ADC
equals
--2----
3
V_DD,
the
ADC
converts
the
signal to $FF (full scale). If the input voltage equals V_SS, the ADC
converts
it
to
$00.
Input
voltage
between
--2----
3
V_DD
and
V_SS
are
a
straight-line linear conversion. All other input voltages will result in $FF
if
greater
than
--2----
3
V_DD
and
$00
if
less
than
V_SS.
NOTE: Input voltage should not exceed the analog supply voltages.
12.4.3 Conversion Time
Twelve ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1MHz, then one conversion will take 12µs to complete.
With a 1MHz ADC internal clock the maximum sample rate is 83.3kHz.
Conversion Time = ^{12 ADC Clock Cycles}
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
12.4.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status control register,
$005D) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
Technical Data
146
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor