MC68HC08BD24 Datasheet, PDF (87/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

7.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configure register 1 (CONFIG1). If the SSREC bit is a logic one, then the
stop recovery is reduced from the normal delay of 4096 OSCXCLK
cycles down to 32 OSCXCLK cycles. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared.
7.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 7.7.2 Stop Mode).
The SIM counter is free-running after all reset states (see 7.4.2 Active
Resets from Internal Sources for counter control and internal reset
recovery sequences).
7.6 Exception Control
Normally, sequential program execution can be changed in three
different ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
87