MC68HC08BD24 Datasheet, PDF (182/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Technical Data
182
The frame frequency is calculated by:
Vertical Frame Frequency
=
------------------------¹--------------------------
VFR ± 1 × 48 × t_CYC
= _V-----_F---_R------_±----¹-₁-----_×----₈----_µ----_s-
for internal bus clock of 6 MHz
Table 14-6 shows examples for the Vertical Frequency Register, all VFR
numbers are in hexadecimal.
Table 14-6. Sample Vertical Frame Frequencies
VFR
$02A0
$03C0
$03C1
$03C2
$04E2
$04E3
$04E4
$06F9
$06FA
$06FB
Max Freq.
186.20 Hz
130.34 Hz
130.21 Hz
130.07 Hz
100.08 Hz
100.00 Hz
99.92 Hz
70.07 Hz
70.03 Hz
69.99 Hz
Min Freq.
185.70 Hz
130.07 Hz
129.94 Hz
129.80 Hz
99.92 Hz
99.84 Hz
99.76 Hz
69.99 Hz
69.95 Hz
69.91 Hz
VFR
$0780
$0823
$0824
$0825
$09C4
$09C5
$09C6
$1FFD
$1FFE
$1FFF
Max Freq.
65.10 Hz
60.04 Hz
60.01 Hz
59.98 Hz
50.02 Hz
50.00 Hz
49.98 Hz
15.266 Hz
15.264 Hz
15.262 Hz
Min Freq.
65.00 Hz
59.98 Hz
59.95 Hz
59.92 Hz
49.98 Hz
49.96 Hz
49.94 Hz
15.262 Hz
15.260 Hz
15.258 Hz
VOF — Vertical Frequency Counter Overflow
This read-only bit is set when an overflow has occurred on the 13-bit
vertical frequency counter. Reset clears this bit, and will be updated
every vertical frame.
An overflow occurs when the period of Vsync frame exceeds
64.768ms (a vertical frame frequency lower than 15.258Hz).
1 = A vertical frequency counter overflow has occurred
0 = No vertical frequency counter overflow has occurred
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor