MC68HC08BD24 Datasheet, PDF (145/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

INTERNAL
DATA BUS
READ DDRC
WRITE DDRC
WRITE PTC
READ PTC
RESET
DDRCx
PTCx
DISABLE
PTCx/ADCx
ADC DATA REGISTER
DISABLE
ADC CHANNEL x
INTERRUPT
LOGIC
CONVERSION
COMPLETE
AIEN COCO
BUS CLOCK
ADC
ADC VOLTAGE IN
ADCVIN
CHANNEL
SELECT
(1 OF 6 CHANNELS)
ADC CLOCK
CLOCK
GENERATOR
ADCH[4:0]
ADIV[2:0] ADICLK
Figure 12-1. ADC Block Diagram
12.4.1 ADC Port I/O Pins
PTC5–PTC0 are general-purpose I/O pins that are shared with the ADC
channels. The channel select bits (ADC status control register, $005D),
define which ADC channel/port pin will be used as the input signal. The
ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O
logic and can be used as general-purpose I/O. Writes to the port register
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
145