MC68HC08BD24 Datasheet, PDF (177/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

14.5.5 Low Vertical Frequency Detect
Logic monitors the value of the Vsync Frequency Register (VFR), and
sets the low vertical frequency flag (LVSIF) when the value of VFR is
higher than $C00 (frequency below 40.7Hz). LVSIF bit can generate an
interrupt request to the CPU when the LVSIE bit is set and I-bit in the
Condition Code Register is "0". The LVSIF bit can help the system to
detect video off mode fast.
14.6 Registers
Eight registers are associated with the Sync Processor, they outlined in
the following sections.
14.6.1 Sync Processor Control & Status Register (SPCSR)
Address: $0040
Bit 7
6
5
4
3
2
1
Bit 0
Read:
VSIF
VSIE VEDGE
Write:
0
VPOL
COMP VINVO HINVO
HPOL
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. Sync Processor Control & Status Register (SPCSR)
VSIE — VSync Interrupt Enable
When this bit is set, the VSIF flag is enabled to generate an interrupt
request to the CPU. When VSIE is cleared, the VSIF flag is prevented
from generating an interrupt request to the CPU. Reset clears this bit.
1 = VSIF bit set will generate interrupt request to CPU
0 = VSIF bit set does not generate interrupt request to CPU
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
177