MC68HC08BD24 Datasheet, PDF (195/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-3 summarizes
the operation of the port A pins.
Table 15-3. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode
0
0
X⁽¹⁾
Input, Hi-Z⁽²⁾
X
1
X
Output
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses
to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
Accesses to PTA
Read
Pin
PTA7–PTA0
Write
PTA7–PTA0⁽³⁾
PTA7–PTA0
15.3.3 Port A Options
The PWM control register 2 (PWMCR2) selects the port A pins for PWM
function or as standard I/O function. See 11.4.2 PWM Control
Registers 1 and 2 (PWMCR1:PWMCR2).
Address: $0059
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E PWM8E
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 15-4. PWM Control Register 1 (PWMCR1)
PWM15E–PWM8E — PWM Output Enable 15–8
Setting a bit to "1" will configure the corresponding PTAx/PWMx pin
for PWM output function. Reset clears these bits.
1 = PTAx/PWMx pin configured as PWMx output pin
0 = PTAx/PWMx pin configured as standard I/O pin
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
195