MC68HC08BD24 Datasheet, PDF (203/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

DDCSCL, DDCSDA — DDC12AB Data and Clock pins
The PTD3/DDCSCL and PTD2/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D configuration register (PDCR) is clear, the
PTD3/DDCSCL and PTD2/DDCSDA pins are available for general-
purpose I/O. See 15.6.3 Port D Options.
15.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
6
5
4
3
2
1
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 15-13. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD6–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD6–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 15-14 shows the port D I/O logic.
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
203