MC68HC08BD24 Datasheet, PDF (22/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

1.3 Features
Features of the MC68HC08BD24 MCU include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 families
• Low-power design; fully static with stop and wait modes
• 5V operating voltage
• 6MHz internal bus frequency, with 24MHz external crystal
• 24,576 + 512 bytes of on-chip read-only memory (ROM)
• 512 bytes of on-chip random access memory (RAM)
• Sync signal processor with the following features:
– Horizontal and vertical frequency counters
– Low vertical frequency indicator (40.7Hz)
– Polarity controlled Hsync and Vsync outputs from separate
sync or composite sync inputs
– Internal generated free-running Hsync and Vsync pulses
– CLAMP pulse output to the external pre-amp chip
• 6-channel, 8-bit analog-to-digital converter (ADC)
• 16-channel, 8-bit pulse width modulator (PWM)
• DDC12AB¹ module with the following:
– DDC1 hardware
– Multi-master IIC² hardware for DDC2AB; with dual address
• 16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, and PWM capability on one
channel
Technical Data
22
1. DDC is a VESA bus standard.
2. IIC is a proprietary Philips interface bus.
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor