MC68HC08BD24 Datasheet, PDF (227/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

18.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register.
18.6 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM Break status register (SBSR)
• SIM Break flag control register (SBFCR)
18.6.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module
enable and status bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-2. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
227