MC68HC08BD24 Datasheet, PDF (186/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

ATPOL — Auto Polarity
This bit, together with the VINVO or HINVO bits in SPCSR controls
the output polarity of the VSYNCO or HSYNCO signals respectively.
Reset clears this bit (see Table 14-9).
Table 14-9. ATPOL, VINVO, and HINVO setting
ATPOL
0
0
1
1
VINVO / HINVO
0
1
0
1
Sync Outputs:
VSYNCO/HSYNCO
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
FSHF — Fast Horizontal Frequency Count
This bit is set to shorten the measurement cycle of the horizontal
frequency. If it is set, only HFH[7:0] and HFL[4:2] will be updated by
the Hsync counter, providing a count in a 8ms window in every
8.192ms, with HFL[1:0] reading as zeros. Therefore, user can
determine the horizontal frequency change within 8.192ms to protect
critical circuitry. Reset clears this bit.
1 = Number of Hsync pulses is counted in an 8ms window
0 = Number of Hsync pulses is counted in a 32ms window
14.6.6 H&V Sync Output Control Register (HVOCR)
Address: $0047
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
R
HVOCR2 HVOCR1 HVOCR0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 14-10. H&V Sync Output Control Register (HVOCR)
Technical Data
186
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor