MC68HC11G5 Datasheet, PDF (96/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
7.6 START BIT DETECTION
When the RXD input is detected low, it is tested for three more sample times (referred to as the start
edge verification samples in Figure 7-5). If at least two of these three verification samples detect a
logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A noise flag
is set if all three verification samples do not detect a logic zero. A valid start bit could be assumed
with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8-bit format or 11 zeros
for 9-bit format), the circuit continues to operate as if there actually was a stop bit and the start edge
will be placed artificially. The last bit received in the data shift register is inverted to a logic one, and
the three logic one start qualifiers (shown in Figure 7-5) are forced into the sample shift register
during the interval when detection of a start bit is anticipated (see Figure 7-6); therefore, the start
bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break produced the framing error, the start bit will not be artificially
induced and the receiver must actually detect a logic one before the start bit can be recognised (see
Figure 7-7).
16X Internal Sampling Clock
RT Clock Edges (For all three Examples)
Idle
RXD
12345678
RRRRRRRR
TTTTTTTT
Start
11111111110
Start
Qualifiers
0
0
0
Start Edge
Verification Samples
RXD
Idle
Start
11111111110
Noise
0
1
0
Idle
RXD
Noise
Start
11110111110
0
0
0
Figure 7-5. Examples of Start Bit Sampling Techniques
SERIAL COMMUNICATIONS INTERFACE
7-6
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