MC68HC11G5 Datasheet, PDF (144/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
any 8-bit value to define when the counter is cleared and the PWM clocked. It causes the PA unit
to act as a prescaler for the PWM by dividing the clock signal, coming via INPUT2, by any value
between 1 and 256.
ECMP2B can be used to generate an interrupt signal EVENT2 after a required number of input
pulses have been accumulated by EVCNT2. If enabled, EVENT2 will interrupt the CPU.
11.5.3 Register Functions in Mode 3
11.5.3.1
Counter 1 (EVCNT1)
EVCNT1 counts the number of pulses coming from the PA unit. It is cleared by a successful
comparison between itself and ECMP1A.
11.5.3.2
Compare Register 1A (ECMP1A)
This compare register holds the value of the PWM period which determines when interrupt 1
(EVENT1) occurs. On a successful comparison with EVCNT1, it generates EVENT1, clears
EVCNT1 and resets output EVO to zero (when EVPOL = 0).
11.5.3.3
Compare Register 1B (ECMP1B)
This compare register holds the PWM duty value which determines when the output (EVO) is set
to one (when EVPOL = 0).
11.5.3.4
DUTY CYCLE = 100 x [1 - (ECMP1B)/(ECMP1A)] %
Counter 2 (EVCNT2)
EVCNT2 counts the number of clock pulses coming from the INPUT2 selector. It is cleared when
a successful comparison occurs between itself and ECMP2A.
11.5.3.5
Compare Register 2A (ECMP2A)
This compare register holds the number of the pulses to be accumulated by EVCNT2 before
EVCNT2 is cleared to zero.
11.5.3.6
Compare Register 2B (ECMP2B)
This compare register holds the number of the pulses to be accumulated by EVCNT2 before an
interrupt signal EVENT2 is generated. If enabled, EVENT2 will interrupt the CPU.
11.5.3.7
Input Unit 1 (EVI1)
This unit is not used and the EVI1 pin (PH5) can be used as a general purpose I/O pin.
11-14
EVENT COUNTER
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