MC68HC11G5 Datasheet, PDF (41/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
controlled by the DDRA bits whether IC3, IC2, and IC1 are enabled or not. Port A bits 3 – 7 are
controlled by the DDRA bits only when the associated output compare functions are disabled.
Enabling an output compare function forces the corresponding port bit to be an output, irrespective
of the state of the DDRA bit. Using any pins of Port A for timer functions has no effect on the ability
to read these pins as inputs (because input sensing logic is always connected to the port pins).
The OC2, OC3, OC4, and OC5 lines out of Port A are enabled by pairs of control bits in the TCTL1
register. The output compare 1 function is unique in that it allows automatic timer control of any
combination of the five most significant bits of Port A regardless of whether or not they are being
used for another timer function. The OC1 function gains control of Port A bits by setting the
corresponding bits in the OC1M control register. The IC1, IC2, IC3, and IC4 input of Port A are
enabled by pairs of control bits in the TCTL2 register. (See SECTION 6: PROGRAMMABLE
TIMER, REAL TIME INTERRUPT AND PULSE ACCUMULATOR.)
The IC4 function and OC5 function share the same Port A bit and they are selected by the I4/O5
bit in the PACTL register. The pulse accumulator system is enabled, on Port A bit 7 as an input, by
setting the PAEN bit in the PACTL register. Even while the pulse accumulator is enabled, Port A bit
7 may be configured as an output controlled by OC1 or as a general purpose output.
4.4.1 Data Register (PORTA )
7
6
5
4
3
2
1
0
$1000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA
RESET:
0
0
0
0
0
0
0
0
Alternate Pin Function: PA1 OC2 OC3 OC4 OC5/IC4 IC1 IC2 IC3
and/or: OC1 OC1 OC1 OC1 OC1 —
—
—
READ: Any time (inputs return pin levels; outputs return pin driver input levels).
WRITE: Data stored in an internal latch. (Drives pins only if configured as outputs.)
RESET: General purpose high impedance inputs ($00).
Note: Writes do NOT change pin state when pin is configured for timer output.
4.4.2 Data Direction Register (DDRA )
$1001
RESET:
7
DDA7
0
6
5
4
DDA6 DDA5 DDA4
0
0
0
3
2
1
DDA3 DDA2 DDA1
0
0
0
0
DDA0
0
DDRA
READ: Any time.
WRITE: Any time.
RESET: $00 (all general purpose I/O configured for input only).
0 – Bits set to zero configure the corresponding I/O pins as inputs.
1 – Bits set to one configure the corresponding I/O pins as outputs.
INPUT/OUTPUT PORTS
4-3
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