MC68HC11G5 Datasheet, PDF (30/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
3.4 MEMORY MAP
Each of the normal and special operating modes of the MC68HC11G5 has a default initial memory
map. In addition, there is a control register (CONFIG) which can be used to remove (disable) the
ROM from the memory map. After reset the INIT register (which is reset to $01 independent of mode
and may only be written under specific circumstances) can alter the mapping of RAM and internal
I/O resources under software control.
While in bootstrap mode, the restart and interrupt vectors are fetched from an alternate memory area
($BFC0 – $BFFF) in an internal bootstrap ROM. In the test mode, vectors are also fetched from the
alternate area ($BFC0 – $BFFF), however, since the bootstrap ROM is not enabled, these vectors
reside in external memory.
Figure 3-1 shows the memory maps for all four modes of operation: single chip, expanded non-
multiplexed, bootstrap and test. On-board memory locations are shown by the shaded areas and
the contents of these areas are described on the right.
3.4.1 Single Chip Mode
This normal operating mode is established by having a logic one level on the MODB/V_kam pin and
a logic zero level on the MODA/LIR pin at the rising edge of RESET. The ROMON bit in the CONFIG
register is a one out of reset in this mode, so that the user ROM appears in the map. The initial
memory map which results is also controlled by the state of three bits (RBOOT, SMOD, and MDA)
in the HPRIO control register which are initialized automatically by hardware prior to the rising edge
on RESET.
Initial conditions affecting the memory map are:
ROMON = 1, RBOOT = 0, SMOD = 0, MDA = 0
MEMORY AND CONTROL/STATUS REGISTERS
3-2
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