MC68HC11G5 Datasheet, PDF (121/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SECTION 10
PULSE WIDTH MODULATION TIMER
10.1 GENERAL OVERVIEW
The PWM module provides up to four 8-bit pulse width modulated waveforms on the Port H pins.
Channel pairs may be concatenated to create 16-bit PWM outputs. Three clock sources (A, B
and S) give the PWM a wide range of frequencies. Figure 10-1 shows the block diagram of the PWM
module.
Each channel also has a separate 8-bit counter register (PWCNTx), period register (PWPERx), and
duty cycle register (PWDTYx). Resetting the counter and starting the waveform output is controlled
by the occurrence of a match between the period register and the value in the counter. Counters
may also be reset by writing to them. The duty register changes the state of the output during the
period to control the duty cycle of the waveform. The period and duty cycle registers are double
buffered so that, if they are changed while the channel is enabled, the change will not take effect
until the counter rolls over or the channel is disabled. A new period or duty cycle can be forced by
writing to the period or duty cycle register and then writing to the counter.
Four control registers are used to configure the PWM outputs – PWCLK, PWPOL, PWSCAL, and
PWEN. The PCKAx and PCKBx bits in the PWCLK register select the prescale values for the PWM
clock sources. PWCLK also contains the CON34 and CON12 bits which enable the 16-bit PWM
functions. The PWPOL register determines each channel’s polarity (PPOLx bits) and selects the
clock source for each channel (PCLKx bits). The PWSCAL register can be programmed with a
prescale value which is used to derive a scaled clock based on the A clock source. The PWENx bits
in the PWEN register enable or disable the PWM channels.
With PWMs configured for 8-bit mode and E = 2 MHz, PWM signals can be produced from 20 kHz
(1% duty cycle resolution) to less than 5 Hz (approximately 0.4% duty cycle resolution). By
configuring the PWMs for 16-bit mode with E = 2 MHz, PWM periods greater than one minute can
be achieved.
In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM
frequency of about 30 Hz). In the same system, a PWM frequency of 1 kHz would correspond to a
duty cycle resolution of 0.05%.
PULSE WIDTH MODULATION TIMER
10-1
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