MC68HC11G5 Datasheet, PDF (75/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
6.4 TIMER, RTI AND PULSE ACCUMULATOR REGISTERS
6.4.1 Count Registers (TCNT1 and TCNT2)
7
6
5
4
3
2
1
0
$100E BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 TCNT1
$100F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Has no effect for SMOD = 0; forces to $FFF8 for SMOD = 1.
RESET: $0000.
7
6
5
4
3
2
1
0
$1052 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 TCNT2
$1053 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Forces to $0000 for SMOD = 0; forces to $FFF8 for SMOD = 1.
RESET: $0000.
TCNT1 is associated with OC1 – OC4, OC5/IC4 and OC6/IC5. Note thatdue to the periodic interrupt
and COP timer also using this counter as their clock source, an external clock cannot be used to
drive this timer counter.
TCNT2 is associated with IC1 – IC3 and OC7/IC6. This counter differs from counter 1 in two ways:
it can be driven by an external clock; and it can be reset under software control.
A full counter read should first address the most significant byte. Reading this address causes the
least significant byte to be latched into a buffer for the next CPU cycle so that a double byte read
will return the full 16-bit state of the counter at the time of the most significant byte read cycle. This
buffer is not affected by reset and is accessed when reading the least significant byte of the counter.
For double byte read instructions, these two accesses occur on consecutive bus cycles. The buffer
is transparent except for the cycle following a most significant byte read so that reads of the least
significant byte alone will return the current state of the counter. Software can read the counter at
any time without affecting its value. Note that the counter is clocked and read during opposite half
cycles of the E-clock.
Both counters are cleared to $0000 during reset. In the normal operating modes (SMOD = 0), writing
to TCNT2 causes TCNT2 to be reset to $0000, whereas writing to TCNT1 has no effect. In the test
and bootstrap modes only (SMOD = 1), any write to either counter’s most significant byte causes
PROGRAMMABLE TIMER
6-5
For More Information On This Product,
Go to: www.freescale.com