MC68HC11G5 Datasheet, PDF (93/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SCI Interrupt
Internal Bus
Transmit
Data Register
(See Note)
Transmit Data
Shift Register
TXD
(PD1)
SCSR
$102E
FE
NF OR IDLE RDRF TC TDRE
SBK
TE
Transmit
Control
7
Flag
Control
Receive
Control
Rate Generator
$102D
SCCR2
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
2
Wake-Up
Unit
Internal
Processor
Clock
$102B TCLR 0 SCP1 SCP0 RCKB SCR2 SCR1 SCR1 BAUD
Receive Data
Register
(See Note)
Receive Data
Shift Register
RXD
(PD0)
$102C R8 T8 0 M WAKE 0 0 0 SCCR1
Figure 7-1. Serial Communications Interface Block Diagram
Note: The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal.
It is the transmit data register when written and the receive data register when read.
SERIAL COMMUNICATIONS INTERFACE
7-3
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