MC68HC11G5 Datasheet, PDF (53/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SECTION 5
RESETS, INTERRUPTS AND LOW POWER MODES
This section describes the internal and external resets and interrupts of the MC68HC11G5 and its
two low power consumption modes.
5.1 RESETS
The MCU can be reset in four ways:
1. An active-low input to the RESET pin
2. A power-on-reset function
3. A clock monitor failure
4. A computer operating properly (COP) watchdog timer timeout
The RESET input circuitry includes a Schmitt trigger which senses the RESET line logic level.
5.1.1 RESET Pin
The RESET pin is used to reset the MCU and allow an orderly software startup procedure. When
a reset condition is sensed, this pin is driven low by an internal device for four E-clock cycles, then
released, and two E-clock cycles later it is sampled. If the pin is still low, it means that an external
reset has occurred. If the pin is high, it implies that the reset was initiated internally by either the
watchdog timer (COP) or the clock monitor. This method of differentiation between internal and
external reset conditions assumes that the reset pin will rise to a logic one in less than two E-clock
cycles once it is released, and that an externally generated reset should stay active for at least eight
E-clock cycles.
5.1.2 Power-on-reset (POR)
Power-on-reset occurs when a positive transition is detected on V_DD. This reset is used strictly for
power turn-on conditions and should not be used to detect any drop in the power supply voltage.
If the external RESET pin is low at the end of the power-on-reset delay time, the processor remains
in the reset state until RESET goes high.
RESETS, INTERRUPTS AND LOW POWER MODES
5-1
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