MC68HC11G5 Datasheet, PDF (50/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Note:
The timer forces the I/O state to be an output if output compare 6 is enabled on Port J
bit 1 (OM6 or OL6 is a 1 and I5/O6 is a 0). The timer also forces the I/O state to be an
output if output compare 7 is enabled on Port J bit 2 (OM7 or OL7 is a 1 and I6/O7 is a
0). In this case, the data direction bit is not changed but has no effect on this line. The
DDRJ bit will revert to controlling the I/O state of the pin when timer output compare 6 is
disabled. TCK does not force the state of the line associated with it.
4.13 EXPANDED BUS (PORTS B, C, F)
The MC68HC11G5 has a non-multiplexed expansion bus. This simplifies system design, as
demultiplexing circuitry is not required. It also eliminates the need for an address strobe line.
The user gains three additional ports when the part is used in single chip mode. Port B provides the
high order addresses in expanded mode, but may be used as a general purpose output port in single
chip mode. Similarly, Port F provides the low order addresses, but may be used as a general purpose
output port in single chip mode. Port C is the data bus in expanded mode, but may be used as general
purpose I/O in single chip mode. Port C has a data direction register for use in single chip mode.
In order to allow emulation of all MC68HC11G5 functions, even in the expanded modes, the
functions displaced by specification of the expanded mode become externally addressed functions.
The registers which become external accesses are PORTC, DDRC, PORTB and PORTF.
4.13.1 R/W
The read/write output signal (R/W) is a dedicated function when the MC68HC11G5 is in normal
expanded mode or test mode. The timing of this signal is the same as the timing for a Port B address
output, except for the hold time from the falling edge of E, which is extended so that no special
circuitry is needed in a multi-board expanded system. This output reflects the state of the internal
CPU R/W signal.
In the single chip and bootstrap modes, the R/W pin is a dedicated output which is always high
(read). This permits changing from one of these modes to an expanded mode, without the risk that
the R/W line might have been in the “write” state, causing bus conflicts or inadvertent external
memory changes.
4-12
INPUT/OUTPUT PORTS
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