MC68HC11G5 Datasheet, PDF (80/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
6.4.7 Output Compare 7/Input Capture 6 Register (TO7I6)
This is a shared register which acts as the output compare OC7 register or as the input capture IC6
register depending on the state of the I6/O7 bit in the TCTL4 register. This register is associated with
timer counter 2 and with Port J, bit 2.
7
6
5
4
3
2
1
0
$1056 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 TO7I6
$1057 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time this register is configured for OC operation.
RESET: $FFFF
There are both input control bits and output control bits associated with these functions. Only the bits
associated with the selected function (input or output) will affect the operation of the timer channel.
6.4.8 Output Compare 1 Action Mask Register (OC1M)
7
6
5
4
3
2
1
0
$100C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0
0
0
OC1M
RESET:
0
0
0
0
0
0
0
0
READ: Any time (bits 2 through 0 always return 0).
WRITE: Any time (writes to bits 2 through 0 have no meaning or effect).
RESET: $00 (OC1 disconnected from Port A logic).
OC1M is used to specify which bits of Port A (I/O and timer port) are to be affected as a result of a
successful OC1 compare. The bits of OC1M correspond bit-for-bit with the bits of Port A. For each
bit to be affected by the successful OC1 compare, the corresponding bit in OC1M must be set to one.
Each Port A line associated with an OC1Mx bit which is set to one will be forced to be an output
regardless of the state of the associated DDRA bit. This does not change the state of the DDRA bit.
6-10
PROGRAMMABLE TIMER
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